After the jump, I'll describe why this is both technically interesting and very important for making chips smaller, more powerful, and less power-hungry.
The semiconductor chips at the heart of nearly all electronics are manufactured on silicon wafers. Today they are typically about 12-inches or 300mm in diameter. Chip generations are measured in nodes, which refer to the width of the smallest features within them. In other words, a 32nm chip, such as today's "Sandy Bridge" set of Intel's "Core" family, has its smallest features at 32nm. The rule of thumb in the semiconductor industry is that the density of a chip--the number of transistors in a given area--doubles every two years. This is known as "Moore's Law" and is based on a paper Intel co-founder Gordon Moore wrote 35 years ago. When technology progresses from 45nm to 32nm or from 32nm to 22nm, it shrinks about 30 percent on each side, with the result being a doubling in the number of transistors.
Typically, memory uses the smallest geometries, as it is easiest to manufacture because each element does exactly the same thing--storing bits. Logic, CPUs or GPUs, is harder, because today's chips have many different kinds of structures for various functions. But underneath all of these are transistors. Note that a quad-core CPU, such as an Intel Sandy Bridge or an upcoming AMD Llano, may have a billion transistors. (For comparison, the 8088 used in the original IBM PC had about 29,000 transistors.)
For most of the history of the semiconductor industry, the majority of the chips were manufactured using fairly standard polysilicon. But as the transistors became smaller, so did the insulating part region of the design, known as the dielectric. In fact, in some designs, the insulating region was only about four atoms thick. As a result, manufacturers were not able to shrink the size of the insulator and had to worry more about "leakage" (where electrons move through the insulating region).
That meant that chip designers had an increasing trade-off between performance and power. They could have a thinner dielectric and higher drive current and thus better performance, but it would have more leakage and thus use more power. Or they could use a thicker dielectric and lower leakage, but less performance.
To combat this, Intel introduced its high-k/metal-gate technology (which replaces silicon dioxide with a thicker insulator that holds the electrical charges better using new materials, such as hafnium) in its transition to 45nm production starting in late 2007. The other big manufacturers are slated to be introducing chips with similar technology in the next couple of months. High-k/metal-gate technology is more complicated to manufacture, but allows for more gate scaling and less leakage.
But during this progress, the transistors themselves have been flat. They're built directly on top of the silicon layer in what the industry calls a "planar" design. But as chip technology continues to scale, the length of the gate and the width of the channel become so small, developers run into other problems.
For years, semiconductor manufacturing conferences have been talking about "non-planar" designs to get around these issues. Most of the papers I've seen are about a transistor with two "gates" (for containing electrons that describe the 1s and 0s that make up the working of a chip) instead of the traditional one. These are often called "FinFETs" (FET for field-effect transistor, the technical name and Fin because the design makes it look a bit like a fin.)
Intel instead has pushed its "Tri-Gate" or 3D transistor technology, which use one horizontal gate above and two on each side of the channel that carry the electrons. With three gates, it has more surface area for the electrons, which Intel says reduces leakage and consumes less power than a traditional transistor or even a FinFET. Intel first discussed this technology in a paper back in 2002 and then presented a significant paper on it in 2006.
The big stumbling block on all of these ideas is the cost and complexity of manufacturing. It would be built on top of the high-k/metal-gate technology. If Intel succeeds in incorporating this design in its 22nm manufacturing process, it would be a big step forward, and it should enable chips that are smaller, while offering better performance at lower power. (Theoretically, an even better solution would be to surround the channel on all sides, creating a "nanowire," but that seems even harder to manufacture.)
Moving from a standard transistor to a "tri-gate" design would be the biggest change in semiconductor manufacturing ever, and it comes at a time when the cost of making new chip factories (or "fabs") is increasing and the number of companies that can afford to actually build such facilities is shrinking. Other than Intel and to a lesser extent Samsung, nearly all logic is now manufactured by "foundries," such as TSMC, UMC, or Globalfoundries. If the transistors really do work as described, it could give Intel a significant advantage in manufacturing in the next few years.
To combat this, Intel introduced its high-k/metal-gate technology (which replaces silicon dioxide with a thicker insulator that holds the electrical charges better using new materials, such as hafnium) in its transition to 45nm production starting in late 2007. The other big manufacturers are slated to be introducing chips with similar technology in the next couple of months. High-k/metal-gate technology is more complicated to manufacture, but allows for more gate scaling and less leakage.
But during this progress, the transistors themselves have been flat. They're built directly on top of the silicon layer in what the industry calls a "planar" design. But as chip technology continues to scale, the length of the gate and the width of the channel become so small, developers run into other problems.
For years, semiconductor manufacturing conferences have been talking about "non-planar" designs to get around these issues. Most of the papers I've seen are about a transistor with two "gates" (for containing electrons that describe the 1s and 0s that make up the working of a chip) instead of the traditional one. These are often called "FinFETs" (FET for field-effect transistor, the technical name and Fin because the design makes it look a bit like a fin.)
Intel instead has pushed its "Tri-Gate" or 3D transistor technology, which use one horizontal gate above and two on each side of the channel that carry the electrons. With three gates, it has more surface area for the electrons, which Intel says reduces leakage and consumes less power than a traditional transistor or even a FinFET. Intel first discussed this technology in a paper back in 2002 and then presented a significant paper on it in 2006.
The big stumbling block on all of these ideas is the cost and complexity of manufacturing. It would be built on top of the high-k/metal-gate technology. If Intel succeeds in incorporating this design in its 22nm manufacturing process, it would be a big step forward, and it should enable chips that are smaller, while offering better performance at lower power. (Theoretically, an even better solution would be to surround the channel on all sides, creating a "nanowire," but that seems even harder to manufacture.)
Moving from a standard transistor to a "tri-gate" design would be the biggest change in semiconductor manufacturing ever, and it comes at a time when the cost of making new chip factories (or "fabs") is increasing and the number of companies that can afford to actually build such facilities is shrinking. Other than Intel and to a lesser extent Samsung, nearly all logic is now manufactured by "foundries," such as TSMC, UMC, or Globalfoundries. If the transistors really do work as described, it could give Intel a significant advantage in manufacturing in the next few years.