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Intel Announces 22nm 3D Tri-Gate Technology, Demonstrates Ivy Bridge

 & Michael J. Miller Former Editor in Chief

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Intel today introduced the first mass-market 3D "Tri-Gate" transistor. It demonstrated the technology running on a 22nm process in a chip known as "Ivy Bridge," due to ship around the end of the year. The Ivy Bridge chip has been long promised, but the 3D technology, which Intel said provides an unprecedented combination of improved performance and energy efficiency, is a big step forward in chip design. Overall, the company said the new technology could increase performance by up to 37 percent or cut power by 50 percent.

Saying "transistors have entered the third dimension," Intel Senior Fellow Mark Bohr explained how until now most transistors have been on a plane, while the new version builds the channel that conduct electrons into the transistors up into the third dimension by using a new design that lets the chips be smaller and denser than it would have been otherwise. (For more details, see my post on the Tri-Gate technology.)

Bohr said this was the world's first demonstration of a 22nm microprocessor, and that this will be the first, high-volume chip to use 3D Tri-Gate transistors.

He said the new technology could have 10 times less leakage and could allow chips with this technology to operate at lower voltages, but have higher performance. He said that a normal shrink to 22nm would have created some performance advantage, but moving to the tri-gate technology at 22nm would allow for a 37 percent increase in transistor gate performance. Alternatively, you could run at the same performance at 0.2 volts less, and combined with better capacitance, it would allow the same performance at a 50 percent power reduction.

Bohr explained that this technology uses "fully depleted" transistors and showed pictures of the transistor with skinny "fins" that create the conducting channel for the electrons. He said that this design allows Intel to vary the number of "fins" (conducting channels) to allow different levels of transistor performance in different parts of the chip. He claimed this technology would only add 2 to 3 percent to the cost of manufacturing a silicon wafer.

Intel Executive VP Dadi Perlmutter held up a wafer that he said contained the 22nm chips and showed off a server, a desktop, and a notebook all running Ivy Bridge chips. On the desktop and mobile versions of the Ivy Bridge chips, he suggested the company would focus on  low-power, high-performance chips with improved graphics and media performance. He said this technology would be entering the market next year, but the company would have more details at an analyst day in two weeks.

Later Perlmutter said users could expect both higher performance chips (although not necessarily with higher frequencies) and those with lower power consumption.

He said the technology would be used in chips ranging from data center chips to those aimed at phones and the embedded market. He promised that Atom chips based on the technology would follow the Ivy Bridge chips, but would allow for smaller, thinner devices with better performance.

When asked about overall performance vs. ARM chips, Perlmutter said the company was not releasing chip benchmarks, but said he believed Intel could compete well on all dimensions, including power consumption. While he said Atom would be behind Ivy Bridge at 22nm, he said Atom was on an "accelerated schedule" and could be manufactured on leading edge technology at about the same time as PC and server processors in the future.

Intel Senior VP for technology and manufacturing Bill Holt said that implementing this technology in its fab was comparable to other changes in materials and structures at other technology nodes.

Bohr added that the entire chip would use the Tri-Gate transistors, with no planar transistors. The technology builds on strained silicon and high-k/metal-gate technology Intel introduced in previous generations. Bohr said he thought Intel would be the only company to use this technology at 22nm, with other companies not likely to use non-planar transistors until 14nm, giving the company at least a three year head start.

About Our Expert

Michael J. Miller

Michael J. Miller

Former Editor in Chief

Michael J. Miller is chief information officer at Ziff Brothers Investments, a private investment firm. From 1991 to 2005, Miller was editor-in-chief of PC Magazine,responsible for the editorial direction, quality, and presentation of the world's largest computer publication. No investment advice is offered in this column. All duties are disclaimed. Miller works separately for a private investment firm which may at any time invest in companies whose products are discussed, and no disclosure of securities transactions will be made.

Until late 2006, Miller was the Chief Content Officer for Ziff Davis Media, responsible for overseeing the editorial positions of Ziff Davis's magazines, websites, and events. As Editorial Director for Ziff Davis Publishing since 1997, Miller took an active role in helping to identify new editorial needs in the marketplace and in shaping the editorial positioning of every Ziff Davis title. Under Miller's supervision, PC Magazine grew to have the largest readership of any technology publication in the world. PC Magazine evolved from its successful PCMagNet service on CompuServe to become one of the earliest and most successful web sites.

As an accomplished journalist, well versed in product testing and evaluating and writing about software issues, and as an experienced public speaker, Miller has become a leading commentator on the computer industry. He has participated as a speaker and panelist in industry conferences, has appeared on numerous business television and radio programs discussing technology issues, and is frequently quoted in major newspapers. His areas of special expertise include the Internet and its applications, desktop productivity tools, and the use of PCs in business applications. Prior to joining PC Magazine, Miller was editor-in-chief of InfoWorld, which he joined as executive editor in 1985. At InfoWorld, he was responsible for development of the magazine's comparative reviews and oversaw the establishment of the InfoWorld Test Center. Previously, he was the west coast bureau chief for Popular Computing, and senior editor for Building Design & Construction. Miller earned a BS in computer science from Rensselaer Polytechnic Institute in Troy, New York and an MS in journalism from the Medill School of Journalism at Northwestern University in Evanston, Illinois. He has received several awards for his writing and editing, including being named to Medill's Alumni Hall of Achievement

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